Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Asynchronous Memory Interface
18-16 ADSP-BF535 Blackfin Processor Hardware Reference
Programmable Timing Characteristics
This section describes the programmable timing characteristics for the
EBIU. Timing relationships depend on the programming of the AMC,
whether initiation is from the core or from MemDMA, and the sequence
of transactions (read followed by read, read followed by write, etc.).
Asynchronous Accesses by Core Instructions
Some external memory accesses are caused by core instructions of the type:
R0 = [P0++] ; /* Read from external memory, where P0 points to
a location in external memory */
or:
[P0++] = R0 ; /* Write to external memory */
Asynchronous Reads
Figure 18-6 shows two core-initiated asynchronous read bus cycles to the
same bank, with timing programmed with setup = 1 cycle, read access = 3
cycles, hold = 2 cycles, and transition time = 1 cycle.
Asynchronous read bus cycles proceed as:
• At the start of the setup period,
AMS[x]
, the address bus, and
ABE[3:0]
become valid, and
AOE
asserts.
• At the beginning of the read access period and after the setup cycle,
ARE
asserts.
• At the beginning of the hold period, read data is sampled on the
rising edge of
CLKOUT
. The
ARE
pin deasserts after this rising edge.