Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 7-3
Chip Bus Hierarchy
SCLK
domain. This divider ratio is set using the
SSEL
parameter of the PLL
Control register. For example, for a 300 MHz core frequency, dividing by
2.5 yields 120 MHz.
These buses can also be cycled at a lower frequency to reduce power con-
sumption. Note that all synchronous peripherals derive their timing from
the
SCLK.
For example, the UART clock rate is determined by further
dividing this clock frequency.
Core Overview
For the purposes of this discussion, Level 1 memories (L1) are included in
the description of the core; they enjoy full bandwidth access from the pro-
cessor core. The core includes the Level 1 (L1) memory subsystem, with
16 KB Instruction SRAM/cache, a dedicated 4 KB Scratchpad SRAM
block, and 32 KB of data SRAM/cache configured as two independent
banks. Except for the Scratchpad, each independent bank can be config-
ured as either SRAM or cache.
The block diagram in Figure 7-2 shows the core processor and its inter-
faces to the SBIU. The core processor is master to these three off-core
interfaces:
• Instruction Fetch (Core I bus), used to fetch 64 bits of instruction
from memory
• Bank0 Load/Store (Core D0 bus), used to write or store 32 bits of
data to or from memory
• Bank1 Load/Store (Core D1 bus), used to write or store 32 bits of
data to or from memory
The core can generate up to three simultaneous off-core accesses per cycle.