Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Servicing Interrupts
4-46 ADSP-BF535 Blackfin Processor Hardware Reference
Core Timer
The Core Timer Interrupt (
IVTMR
) is triggered when the core timer value
reaches zero. See “Timers” on page 16-1 .
General-Purpose Interrupts (IVG7-IVG15)
General-purpose interrupts are used for any event that requires processor
attention. For instance, a DMA controller may use them to signal the end
of a data transmission, or a serial communications device may use them to
signal transmission errors.
Software can also trigger general-purpose interrupts by using the
RAISE
instruction. The
RAISE
instruction can force events for interrupts
IVG15-IVG7
,
IVTMR
,
IVHW
,
NMI
, and
RST
, but not for exceptions and emula-
tion (
EVX
and
EMU
, respectively).

It is recommended to reserve the two lowest priority interrupts
(
IVG15
and
IVG14
) for software interrupt handlers.
Servicing Interrupts
The CEC has a single interrupt queueing element per event, as a bit in the
ILAT
register. The appropriate
ILAT
bit is set when an interrupt rising edge
is detected (which takes 2 core clock cycles) and cleared when the respec-
tive
IPEND
register bit is set. The
IPEND
bit indicates that the event vector
has entered the core pipeline. At this point, the CEC recognizes and
queues the next rising edge event on the corresponding interrupt input.
The minimum latency from the rising edge transition of the general-pur-
pose interrupt to the
IPEND
output asserted is three core clock cycles.
However, the latency can be much higher, depending on the core’s activ-
ity level and state.