Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 378 / 1022

DMA Control Registers
9-18 ADSP-BF535 Blackfin Processor Hardware Reference
Table 9-4 lists the MMR assignments for the peripheral DMA Configura-
tion registers.
The Descriptor Block Ownership (
DBO
) bit can be set only when bit 15 of a
descriptor block’s DMA Configuration Word is set and the DMA Config-
uration Word is loaded into the peripheral’s
DMA Configuration register.
When the current DMA transfer sequence has completed, the DMA chan-
nel clears bit 15 in the peripheral’s
DMA Configuration register and
writes the contents of the register to the current descriptor block’s Config-
uration Word in memory. Then the next descriptor block’s Configuration
Word is loaded into the peripheral’s
DMA Configuration register. If bit
15 of the Configuration Word is set (DMA channel has ownership), a full
descriptor block download is performed, and bit 15 of the peripheral’s
DMA Configuration register is set once again.
Table 9-4. Peripheral DMA Configuration Register MMR Assignments
Register Name Memory-Mapped Address
SPI0_CONFIG 0xFFC0 3202
SPI1_CONFIG 0xFFC0 3602
SPORT0_RX_CONFIG 0xFFC0 2802
SPORT1_RX_CONFIG 0xFFC0 2C02
SPORT0_TX_CONFIG 0xFFC0 2800
SPORT1_TX_CONFIG 0xFFC0 2C00
UART0_CONFIG_RX 0xFFC0 1A02
UART1_CONFIG_RX 0xFFC0 1E02
UART0_CONFIG_TX 0xFFC0 1B02
UART1_CONFIG_TX 0xFFC0 1F02
USBD_DMACFG 0xFFC0 4440