Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-47
External Bus Interface Unit
SDQM Operation
The
SDQM[3:0]
(Data I/O Mask) pins enable the SDC to mask off bytes
during byte and half word (two-byte) write transfers. For write cycles, the
data masks have a latency of zero cycles, permitting data writes when the
corresponding
SDQM[x]
pin is sampled low and blocking data writes when
the
SDQM[x]
pin is sampled high on a byte-by-byte basis. The
SDQM[x]
pin
should be asserted during Precharge.
Executing a Parallel Refresh Command
The SDC includes a separate address pin (
SA10
) to enable the execution of
Auto-Refresh commands in parallel with any asynchronous memory
access. This separate pin allows the SDC to Precharge the SDRAM before
it issues an Auto-Refresh command. In addition, the
SA10
pin allows the
SDC to enter and exit Self-Refresh mode in parallel with any asynchro-
nous memory access.
The
SA10
pin should be directly connected to the
A10
pin of the SDRAM
(instead of to the
ADDR[10]
pin). During the Precharge command,
SA10
is
used to indicate that a Precharge All should be done. During a Bank Acti-
vate command,
SA10
outputs the internal row address bit, which should be
multiplexed to the
A10
SDRAM input. During Read and Write com-
mands,
SA10
is used to disable the auto-precharge function of SDRAMs.
Selecting the Bank Activate Command Delay (TRAS)
The t
RAS
value (Bank Activate command delay) defines the required delay,
in number of
SCLK
cycles, between the time the SDC issues a Bank Acti-
vate command and the time it issues a Precharge command. The SDRAM
must also remain in Self-Refresh mode for a period of time of at least t
RAS
.
The t
RP
and t
RAS
values define the t
RFC
, t
RC
, and t
XSR
values. See the
t
RFC
, t
RC
, and t
XSR
descriptions on page 18-36 for more information.