Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 8-23
Dynamic Power Management
in the bit enables clocking to that peripheral; a 0 in the bit turns off
clocking to that peripheral. This register can be altered at any time in any
operating mode.
After a reset, the
PLL_IOCK
register defaults to enable clocking for all
peripherals.
Dynamic Supply Voltage Control
In addition to clock frequency control, the ADSP-BF535 processor pro-
vides the capability to run the core processor at different voltage levels. As
power dissipation is proportional to the voltage squared, significant power
reductions can be accomplished when lower voltages are used.
The ADSP-BF535 processor uses five power domains. These power
domains are shown in
Table 8-6 . Each power domain has a separate V
DD
supply. Note the internal logic of the processor and much of the processor
I/O can be run over a range of voltages. See
ADSP-BF535 Blackfin Embed-
ded Processor Data Sheet for details on the allowed voltage ranges for each
power domain and power dissipation data.
Figure 8-6. Peripheral Clock Enable Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset = 0xFFFF
Peripheral Clock Enable Register (PLL_IOCK)
0 = Disabled, 1 = Enabled
SPI0 Clock
SPORT1 Clock
SPORT0 Clock
Memory DMA Clock
PF Clock
EBIU Clock
PCI Clock
SPI1 Clock
UART0 Clock
UART1 Clock
Timer 0, 1, 2 Clock
USB Clock
0xFFC0 0408