Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 11-13
Serial Port Controllers

The
TFSR
bit is normally set. A frame sync pulse is used to mark the
beginning of each word or data packet, and most systems need
frame sync to function properly.
• Data Independent Transmit Frame Sync Select.
SPORTx_TX_CONFIG[11]
(
DITFS
). This bit selects whether the
SPORT uses a data independent
TFS
(sync at selected interval, if
set) or uses a data dependent
TFS
(sync when data in
SPORTx_TX
, if
cleared).
The frame sync pulse marks the beginning of the data word. If
DITFS
is set, the frame sync pulse is issued on time, whether the
TX
register has been loaded or not; if
DITFS
is cleared, the frame sync
pulse is only generated if the
TX
data register has been loaded. If the
receiver demands regular frame sync pulses,
DITFS
should be set,
and the core should keep loading the
SPORTx_TX
register on time. If
the receiver can tolerate occasional late frame sync pulses,
DITFS
should be cleared to prevent the SPORT from transmitting old
data twice or transmitting garbled data if the core is late in loading
the
TX
register.
• Low Transmit Frame Sync Select.
SPORTx_TX_CONFIG[12]
(
LTFS
).
This bit selects an active low
TFS
(if set) or active high
TFS
(if
cleared).
• Late Transmit Frame Sync.
SPORTx_TX_CONFIG[13]
(
LATFS
). This
bit configures late frame syncs (if set) or early frame syncs (if
cleared).
• Clock Drive/Sample Edge Select.
SPORTx_TX_CONFIG[14]
(
CKFE
).
This bit selects which edge of the
TCLKx
signal the SPORT uses for
driving data, for driving internally generated frame syncs, and for
sampling externally generated frame syncs. If set, data and inter-
nally generated frame syncs are driven on the falling edge and
externally generated frame syncs are sampled on the rising edge.