Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Dynamic Power Management Controller
8-16 ADSP-BF535 Blackfin Processor Hardware Reference
In addition to the mode transitions shown in Figure 8-5 , the PLL can be
modified while in the Active operating mode. Power to the PLL can be
applied and removed, and new clockin (
CLKIN
) to core clock (
CCLK
) multi-
plier ratios can be programmed. Described in detail below, these changes
to the PLL do not take effect immediately. As with operating mode
transitions, the PLL programming sequence must be executed for these
changes to take effect. See “PLL Programming Sequence” on page 8-17 :
• PLL Disabled: In addition to being bypassed in the Active mode,
power to the PLL can be removed. When power is removed from
the PLL, additional power savings are achieved although they are
relatively small. To remove power to the PLL, set the
PLL_OFF
bit
in the
PLL_CTL
register, and then execute the PLL programming
sequence.
• PLL Enabled: When the PLL is powered down, power can be reap-
plied later when additional performance is required. Power to the
PLL must be reapplied before transitioning to the Full On or Sleep
operating modes. To apply power to the PLL, clear the
PLL_OFF
bit
in the
PLL_CTL
register, and then execute the PLL programming
sequence.
• New Multiplier Ratio: New clockin (
CLKIN
) to core clock (
CCLK
)
multiplier ratios can be programmed while in the Active mode.
Although the
CLKIN
to
CCLK
multiplier changes are not realized in
the Active mode, forcing the PLL to lock to the new ratio in the
Active mode before transitioning to Full On reduces the transition
time, because the PLL is already locked to the new ratio. Note that
the PLL must be powered up to lock to the new ratio. To program
a new
CLKIN
to
CCLK
multiplier, write the new
MSEL[6:0]
and/or
DF
values to the
PLL_CTL
register; then execute the PLL programming
sequence.