Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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External Memory Design Issues
19-12 ADSP-BF535 Blackfin Processor Hardware Reference
Example SDRAM Interfaces
Figure 19-5 shows a block diagram of the ADSP-BF535 processor’s
SDRAM interface. In this example, the SDRAM interface connects to
four 64 Mbit (x8) SDRAM devices, to form one external bank of 32
Mbytes of memory. The same address and control bus feeds all four
SDRAM devices.
The ADSP-BF535 processor’s SDRAM controller supports industry stan-
dard 32-bit and 64-bit wide data bus DIMMs. These DIMMs generally
have multiple chip select inputs with each connected to a portion of the
chips on the DIMM. Most DIMMs can be interfaced to the ADSP-BF535
processor gluelessly by using the
SMS[3:0]
bank selects, the
SDQM[3:0]
data masks, and careful connection of the data bus.
Divide the DIMM into multiple banks and connect it based on the
SDRAM chip enables. Since the data bus is only 32 bits wide at the most,
64-bit DIMMs must be connected as two banks. Note the range of num-
bers for the
DQM
and
DATA
signals on the SDRAM DIMM may not match
the corresponding range on the ADSP-BF535 processor.
64 16 256
8M

8

4banks
2 10
64 16 512
8M

16

4banks
1 10
128 16 256
16M

4

4banks
4 11
128 16 512
16M

8

4banks
2 11
Table 19-1. SDRAM Discrete Component Configurations
Supported (Cont’d)
Bank Size
(MByte) Bank
Width
(Bits) SDRAM
Size (Mbit) Configuration Number of
Chips Number of
Column Address
Pins