Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 11-41
Serial Port Controllers
DMA Enable bit in the Transmit DMA Configuration registers, shown in
Figure 11-25 . The DMA Configuration register maintains real time DMA
buffer status.
Each SPORT DMA channel has an enable bit (
DEN
) in these registers for
each of the serial ports. When DMA is not enabled for a particular chan-
nel, the SPORT generates an interrupt every time it starts to transmit a
data word.
When the Interrupt on Completion bit of the
SPORTx_CONFIG_DMA_TX
reg-
ister is set, bit 0 of the
SPORTx_IRQSTAT_TX
register is set and a DMA
interrupt is generated after the final transfer of data. Final transfer of data
occurs when DMA count = 0, as specified by the descriptor work block.
DMA transfer size can be set to 8, 16, or 32 bits. This provides flexibility
in how data is packed in memory. For DMA writes to memory in excess of
the 16-bit FIFO size, the upper bits are padded with zeros. For DMA
writes to memory smaller than the 16-bit FIFO size, only the LSBs of the
FIFO are written. A DMA read of memory greater than the 16-bit FIFO
size reads only the LSBs of memory into the FIFO. For DMA reads of
memory smaller than the FIFO size, the least significant bits of the FIFO
are loaded and the remaining FIFO bits have unknown values. DMA data
transfer size is determined by setting the Data Size Bit 0 and Data Size Bit
1 bits in the
SPORTx_CONFIG_DMA_TX
register.
When the Interrupt on Error bit is set, a transmit underflow error results
in bit 1 of the
SPORTx_IRQSTAT_TX
register being set and a DMA interrupt
being generated.
The Transmit Underflow Error bit is set if an underflow condition occurs.
This bit is sticky only during the current work block. It is cleared on the
next descriptor fetch.