Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 4-45
Program Sequencer
• Peripheral errors
• Bus timeout errors
The list of supported hardware conditions, with their related
HWERRCAUSE
codes, appears in Table 4-13 . The bit code for the most recent error
appears in the
HWERRCAUSE
field. If multiple hardware errors occur simulta-
neously, only the last one can be recognized and serviced. The core does
not support prioritizing, pipelining, or queuing multiple error codes. The
hardware error interrupt remains active as long as any of the error condi-
tions remain active.
Table 4-13. Hardware Conditions Causing Hardware Error Interrupts
Hardware
Condition HWERRCAUSE
(binary) HWERRCAUSE
(hexadecimal) Notes / Examples
DMA Bus
Comparator
Source 0b00001 0x01 The Compare Hit output is
routed directly to the Hardware
Error interrupt input. The Com-
pare Hit interrupt is maskable by
writing to the DMA Bus Control
Comparator register (
DB_CCOMP
).
See “DMA Bus Debug Registers”
on page 20-27 .
Performance
Monitor
Overflow 0b10010 0x12 Refer to “Performance Monitor-
ing Unit” on page 20-19 .
Error accessing
reserved or unde-
fined memory 0b10110 0x16 An access to reserved or uninitial-
ized memory was attempted
Error accessing
reserved or unde-
fined memory 0b10111 0x17 An access to reserved or uninitial-
ized memory was attempted
RAISE
instruction 0b11000 0x18 Software issued a
RAISE
instruc-
tion to invoke the hardware error
interrupt (
IVHW
).
Reserved All other bit combi-
nations. All other bit combi-
nations.