Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 16-27
Timers
The
WDOG_STAT
register is a 32-bit unsigned system MMR that must be
accessed with 32-bit reads and writes.
Watchdog Control Register (WDOG_CTL)
The Watchdog Control register (
WDOG_CTL
), shown in Figure 16-20 , is a
16-bit system MMR used to control the watchdog timer.
The
ICTL[1:0]
field is used to select the event that is generated when the
watchdog timer expires. Note that if the general-purpose interrupt option
is selected, the System Interrupt Mask register (
SIC_IMASK
) should be
appropriately configured to unmask that interrupt. If the generation of
watchdog events is disabled, the watchdog timer operates as described,
except that no event is generated when the watchdog timer expires.
The
TMR_EN[3:0]
field is used to enable and disable the watchdog timer.
Writing any value other than the disable value into this field enables the
watchdog timer. This multibit disable key minimizes the chance of inad-
vertently disabling the watchdog timer.
Figure 16-19. Watchdog Status Register
Watchdog Status Register (WDOG_STAT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset = 0x0000 0000
Watchdog Status[31:16]
Watchdog Status[15:0]
0xFFC0 1008