Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 10-33
SPI Compatible Port Controllers
If the transmit buffer remains empty or the receive buffer remains full, the
device operates according to the states of the
SZ
and
GM
bits in
SPIx_CTL
. If
SZ = 1
and the transmit buffer is empty, the device repeatedly transmits 0s
on the
MOSI
pin. One word is transmitted for each new transfer initiate
command. If
SZ = 0
and the transmit buffer is empty, the device repeat-
edly transmits the last word it transmitted before the transmit buffer
became empty. If
GM = 1
and the receive buffer is full, the device contin-
ues to receive new data from the
MISO
pin, overwriting the older data in
the
SPIx_RDBR
buffer. If
GM = 0
and the receive buffer is full, the incoming
data is discarded and
SPIx_RDBR
is not updated.
Transfer Initiation From Master (Transfer Modes)
When a device is enabled as a master, the initiation of a transfer is defined
by the two
TIMOD
bits of
SPIx_CTL
. Based on those two bits and the status
of the interface, a new transfer is started upon either a read of
SPIx_RDBR
or a write to
SPIx_TDBR
. Transfer initiation is summarized in Table 10-19 .
Table 10-19. Transfer Initiation
TIMOD Function Transfer Initiated Upon Action, Interrupt
00 Transmit and
Receive Initiate new single-word trans-
fer upon read of SPIx_RDBR
and previous transfer com-
pleted Interrupt active when receive
buffer is full
Read of SPIx_RDBR clears
interrupt
01 Transmit and
Receive Initiate new single-word trans-
fer upon write to SPIx_TDBR
and previous transfer com-
pleted Interrupt active when transmit
buffer is empty
Writing to SPIx_TDBR clears
interrupt