Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 4-7
Program Sequencer
Instruction Pipeline
The Program Sequencer determines the next instruction address by exam-
ining both the current instruction being executed and the current state of
the processor. If no conditions require otherwise, the processor executes
instructions from memory in sequential order by incrementing the look
ahead address.
The ADSP-BF535 processor has an eight-stage instruction pipeline,
shown in
Figure 4-4 .
Figure 4-4. ADSP-BF535 Processor Pipeline
Table 4-3. Stages of Instruction Pipeline
Pipeline Stage Description
Instruction Fetch 1 (IF1) Start instruction memory access.
Instruction Fetch 2 (IF2) Finish L1 instruction memory access and align
instruction.
Instruction Decode (DEC) Start instruction decode and access Pointer register file.
Address Calculation (AC) Calculate data addresses and branch target address.
Execute 1 (EX1) Read data and start access of data memory.
Execute 2 (EX2) Finish accesses of data memory and start execution of
dual cycle instructions.
Execute 3 (EX3) Execute single cycle instructions.
Write Back (WB) Write states to Data and Pointer register files and process
events.
Inst
Fetch 1
Inst
Fetch 2
Inst
Decode
Address
Calc
Ex1
Ex2 Ex3
WB
Inst
Fetch 1
Inst
Fetch 2
Inst
Decode
Address
Calc
Ex1
Ex2 Ex3
WB