Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-31
External Bus Interface Unit
CAS Latency (also t
AA
, t
CAC
, CL).
The column address strobe (CAS) latency is the delay in clock cycles
between when the SDRAM detects the read command and when it pro-
vides the data at its output pins. The CAS latency is programmed in the
SDRAM Mode register during the power-up sequence.
The speed grade of the SDRAM and the
SCLK[0]
frequency determine the
value of the CAS latency. The SDC can support CAS latency of 2 or 3
clock cycles. The selected CAS latency value must be programmed into
the SDRAM Memory Global Control register (
EBIU_SDGCTL
) before the
SDRAM power-up sequence. See “SDRAM Memory Global Control Reg-
ister (EBIU_SDGCTL)” on page 18-37 .
CBR (CAS before RAS) Refresh or Auto-Refresh.
When the SDC refresh counter times out, the SDC precharges all four
banks of SDRAM and then issues an Auto-Refresh command to them.
This causes the SDRAMs to generate an internal CBR refresh cycle. When
the internal refresh completes, all four SDRAM banks are precharged.
DQM Data I/O Mask Function.
The
SDQM[3:0]
pins provide a byte-masking capability on 8- or 16-bit
writes to SDRAM. The
DQM
pins are used to block the output buffer of the
SDRAM during precharge and certain write operations. The
SDQM[3:0]
pins are not used to mask data on read cycles. For 16-bit wide SDRAM,
only
SDQM[1:0]
are needed for byte masking.
Internal Bank.
There are several internal memory banks on a given SDRAM row. An
internal bank in a specific row cannot be activated (opened) until the pre-
vious internal bank in that row has been precharged.