Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-21
External Bus Interface Unit
Asynchronous Writes Followed by Reads
Figure 18-9 shows an asynchronous write bus cycle followed by two asyn-
chronous read cycles to the same bank, with timing programmed with
setup = 1 cycle, write access = 2 cycles, read access = 2 cycles, hold = 2
cycles, and transition time = 1 cycle.
The asynchronous write bus cycles proceed as:
• At the start of the setup period,
AMS[x]
, the address bus, data buses,
and
ABE[3:0]
become valid.
• At the beginning of the write access period,
AWE
asserts.
• At the beginning of the hold period,
AWE
deasserts and
AMS[x]
remains low for the setup period of the next access.
The first asynchronous read bus cycle proceeds as:
• At the start of the setup period,
AMS[x]
is still asserted. The address
bus, and
ABE[3:0]
become valid, and
AOE
asserts.
• At the beginning of the read access period,
ARE
asserts.
• At the beginning of the hold period, read data is sampled on the
rising edge of the EBIU clock. The
ARE
pin deasserts after this ris-
ing edge.
• At the end of the hold period,
AOE
and
AMS[x]
deassert.
The second asynchronous read bus cycle proceeds as:
• At the start of the setup period,
AMS[x]
, the address bus, and
ABE[3:0]
become valid, and
AOE
asserts.
• At the beginning of the read access period,
ARE
asserts again.