Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 187 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 4-41
Program Sequencer
Data access mis-
aligned address viola-
tion 0x24 E Attempted misaligned data memory
or data cache access.
Unrecoverable event 0x25 E For example, an exception generated
while processing a previous exception.
Data access CPLB miss 0x26 E Used by the MMU to signal a CPLB
miss on a data access.
Data access multiple
CPLB hits 0x27 E More than one CPLB entry matches
data fetch address.
Exception caused by
an emulation watch-
point match 0x28 E There is a watchpoint match, and one
of the EMUSW bits in the Watch-
point Instruction Address Control
register (
WPIACTL
) is set.
Instruction fetch
access exception 0x29 E Error from instruction fetch, for
example, instruction bus parity error.
Instruction fetch mis-
aligned address viola-
tion 0x2A E Attempted misaligned instruction
cache fetch. On a misaligned instruc-
tion fetch exception, the return
address provided in
RETX
is the desti-
nation address which is misaligned,
rather than the address of the offend-
ing instruction. For example, if an
indirect branch to a misaligned
address held in
P0
is attempted, the
return address in
RETX
is equal to
P0
,
rather than to the address of the
branch instruction. (Note that this
exception can never be generated
from PC-relative branches, only from
indirect branches.)
Instruction fetch
CPLB protection vio-
lation 0x2B E Illegal instruction fetch access (mem-
ory protection violation).
Table 4-11. Events That Cause Exceptions (Cont’d)
Exception EXCAUSE[5:0] Type:
(E) error
(S) service
See note 1. Notes/Examples