Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-77
Memory
Figure 6-31 shows 16-bit and 32-bit instructions stored in memory. The
diagram on the left shows how 16-bit instructions are stored in memory
with the most significant byte of the instruction stored in the high address
(byte B1 in
addr+1 ) and the least significant byte in the low address (byte
B0 in addr ).
The diagram on the right shows how 32-bit instructions are stored in
memory. The most significant 16-bit half word of the instruction (bytes
B3 and B2) is stored in the low addresses (
addr+1 and addr ), and the least
significant half word (bytes B1 and B0) is stored in the high addresses
(
addr+3 and addr+2 ).
Load/Store Operation
The Blackfin processor architecture supports the RISC concept of a
Load/Store machine. This machine is the characteristic in RISC architec-
tures whereby memory operations (loads and stores) are intentionally
separated from the arithmetic functions that use the targets of the memory
operations. The separation is made, because memory operations, particu-
larly instructions that access off-chip memory or I/O devices, often take
multiple cycles to complete and would normally halt the processor, pre-
venting an instruction execution rate of one instruction per cycle.
Figure 6-31. Instructions Stored in Little Endian Order
16-BIT INSTRUCTIONS IN MEMORY 32-BIT INSTRUCTIONS IN MEMORY
B1 B0 B1 B0 B1 B0 B3 B2
addr+3 addr+2
addr+1
addr
addr+3 addr+2
addr+1
addr
16-BIT INSTRUCTIONS 32-BIT INSTRUCTIONS
B1 B0 B3 B2 B1 B0
INST 0 INST 0