Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference A-1
A BLACKFIN PROCESSOR
CORE MMR ASSIGNMENTS
The Blackfin processor’s memory-mapped registers are in the address
range 0xFFE0 0000–0xFFFF FFFF. All MMRs are 32-bits and can be
accessed only with 32-bit aligned memory operations.
This appendix lists core MMR addresses and register names. To find more
information about an MMR, refer to the page shown in the “See Section”
column. When viewing the PDF version of this document, click a refer-
ence in the “See Section” column to jump to the additional information
about the MMR.
L1 Data Memory Controller Registers
Table A-1 lists the MMR assignments for the L1 Data Memory Controller
registers (0xFFE0 0000–0xFFE0 0040C).
Table A-1. L1 Data Memory Controller Registers
Memory- Mapped
Address Register Name See Section
0xFFE0 0004 DMEM_CONTROL “Data Memory Control Register
(DMEM_CONTROL)” on page 6-12
0xFFE0 0008 DCPLB_STATUS “DCPLB Status Register
(DCPLB_STATUS)” on page 6-73
0xFFE0 000C DCPLB_FAULT_ADDR “DCPLB Fault Address Register
(DCPLB_FAULT_ADDR)” on page 6-75
0xFFE0 0100 DCPLB_ADDR0 “DCPLB Address Registers
(DCPLB_ADDRx)” on page 6-69