Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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System Interfaces
7-14 ADSP-BF535 Blackfin Processor Hardware Reference
In the case where the transfer is from on-chip to on-chip memory or from
off-chip to off-chip memory, the burst accesses cannot occur simultane-
ously. The transfer rate is then determined by adding each transfer plus an
additional cycle between each transfer.
Table 7-4 shows an example of two types of memory DMA transfers.
DAB Bus Agents (Masters)
All peripherals capable of sourcing a DMA access are masters on this bus,
as shown in the DAB arbitration priorities in
Table 7-2 . A single arbiter
supports a fixed priority arbitration policy for access to the DAB.
External Access Bus (EAB)
The EAB provides a way for the processor core and the Memory DMA
controller to directly access off-chip memory and the PCI memory space
to perform instruction fetches, data loads, data stores, and high through-
put memory-to-memory DMA transfers.
Table 7-4. Memory DMA Transfer Rates
Description of Transfer Primary Burst of
8 Access in
SCLKs Secondary Burst
of 8 Access in
SCLKs Total SCLKs
Burst of 8 Transfer from SDRAM to
L1
(Off-chip to On-chip Memory Trans-
fer) 19 Cycles (L1) 16 Cycles
(SDRAM) 21 (19+2)
Burst of 8 Transfer from L2 to L1
(On-chip to On-chip Memory Trans-
fer) 19 Cycles (L1) 12 Cycles (L2) 33 (19+12+2)