Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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System Interfaces
7-18 ADSP-BF535 Blackfin Processor Hardware Reference
External Mastered Bus (EMB)
The EMB provides a means for the PCI to directly access internal L2
memory, off-chip memory, and the system MMRs.
EMB Arbitration
For ADSP-BF535 processors, only the PCI controller can master this bus.
EMB Performance
The EMB supports single word accesses of either 8-bit, 16-bit or 32-bit
data types. The EMB operates at the same frequency as the PAB and the
DAB.
The EMB supports access to the external memory space. PCI-mastered
accesses to internal L2 memory have higher priority than core accesses to
the same bank, unless the core has the memory lock asserted, or the core is
in the middle of a burst.
The EMB provides access to memory-mapped registers from the PCI.
Access to the system MMRs through the SBIU to the PAB is deterministic
and always requires 3
SCLK
cycles for the first read, requiring 1 wait state.
Writes require no wait states and are fully pipelined. Burst access is not
supported.
EMB Bus Agents (Masters, Slaves, Bridges)
The PCI is the only master on this bus. The SBIU and EBIU are the slaves
on this bus. The PCI controller is a bridge between the EMB and the PCI
buses.