Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-1
6 MEMORY
The ADSP-21535 processor supports a hierarchical memory model with
different performance and size parameters, depending on the memory
location within the hierarchy. Level 1 (L1) memories are faster memories
located closer to the processor core, whereas Level 2 (L2) memories are
memory systems farther from the core, typically with longer access laten-
cies. The faster L1 memories, which include an instruction, data, and
scratchpad memory as part of the Blackfin core, are accessed in a single
cycle. The L2 memories, which include an on-chip SRAM and off-chip
mapping to synchronous, asynchronous and PCI devices, provide much
larger memory spaces with higher latencies.
The focus of this chapter is on-chip L1 and L2 memory. The off-chip L2
memory is explained in more detail in
“External Bus Interface Unit” on
page 18-1 . The PCI memory space, which is also part of the off-chip L2
memory, is further described in “PCI Bus Interface” on page 13-1 .
Terminology
The following terminology is used to describe memory.
cache block.
The smallest unit of memory that is transferred to/from the next level of
memory from/to a cache as a result of a cache miss.
cache hit.
A memory access that is satisfied by a valid, present entry in the cache.