ADSP-BF535 Blackfin Processor Hardware Reference
7-9
Chip Bus Hierarchy
PAB Agents (Masters, Slaves)
The processor core and the PCI controller can master bus operations on
the PAB, through the SBIU. All peripherals have a peripheral bus slave
interface which allows the processor core to access control and status state.
These registers are mapped into the system MMR space of the memory
map. System MMR addresses are listed in
Appendix A, “Blackfin Proces-
sor Core MMR Assignments”
and
Appendix B, “System MMR
Assignments”
.
The slaves on the PAB bus are as follows:
• Event Controller
• Emulation/Test Control
• Clock and Power Management Controller
• Watchdog Timer
• Real Time Clock
• Timer 0, 1, and 2
• SPORT0
• SPORT1
• SPI0
• SPI1
• Programmable Flags
• UART0
• UART1
• USB
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...