Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 4-5
Program Sequencer
Zero-Overhead Loop Registers (LC, LT, LB)
Two sets of zero-overhead loop registers implement loops, using hardware
counters instead of software instructions to evaluate loop conditions. After
evaluation, processing branches to a new target address. Both sets of regis-
ters include the Loop Counter (
LC
), Loop Top (
LT
), and Loop Bottom
(
LB
) registers.
Figure 4-2. Sequencer Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sequencer Status Register (SEQSTAT)
IDLE_REQ
EXCAUSE[5:0]
Holds information about the
last-executed exception. See
Table 4-11 .
This bit is set by the IDLE
instruction.
0 - No pending request for
idle state
1 - Pending request for idle
state
Reset = 0x0000 0X00
HWERRCAUSE[1:0]
Holds cause of last hardware error
generated by the core. Hardware
errors trigger interrupt number 5
(IVHW).
0x12 - Performance Monitor
overflow
0x15 - Reserved
0x16 - Error accessing reserved or
undefined memory
0x17 - Error accessing reserved or
undefined memory
0x18 - Instruction RAISE
All other values - Reserved
SFTRESET
0 - Last core reset was not a
software-triggered reset
1 - Last core reset was a soft-
ware-triggered reset, rather
than a hardware power-up
reset
HWERRCAUSE[4:2]
See description under bits [1:0],
below