Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 7-13
Chip Bus Hierarchy

The PCI controller, the core processor, and the DAB must arbi-
trate for access to external memory through the EBIU. This
additional arbitration latency added to the latency required to read
off-chip memory devices can significantly degrade DAB through-
put, potentially causing peripheral data buffers to underflow or
overflow. If you use DMA peripherals other than the Memory
DMA controller, and you target external memory for DMA
accesses, you need to carefully analyze your specific traffic patterns
to ensure that those isochronous peripherals targeting internal
memory have enough allocated bandwidth and the appropriate
maximum arbitration latencies.
When two or more DMA master channels are actively requesting the
DAB, bus utilization is considerably higher due to the DAB’s pipelined
design. Bus arbitration cycles are concurrent with the previous DMA
access’s data cycles.
Memory DMA transfers typically result in repeated accesses to the same
memory location. Because the memory DMA controller has the potential
of simultaneously accessing on-chip and off-chip memory, considerable
throughput can be achieved. The throughput rate for an on-chip/off-chip
memory access is limited by the slower of the two accesses. An additional
1 to 2 cycles per burst access is inherent in the design.
Burst Read from External Mem-
ory (SDRAM)
(16-byte and 32-byte) All ratios 9-1-1-1 9-1-1-1-1-1-1-1
Write to SDRAM (burst of 8) All ratios 4-2-2-2 4-2-2-2-2-2-2-2
Burst Read from Async Memory All ratios 12-4-4-4 12-4-4-4-4-4-4-4
Burst Write to Async Memory All ratios 12-4-4-4 12-4-4-4-4-4-4-4
Table 7-3. DAB Latencies (Cont’d)
Use of DAB Core Clock to System
Clock Ratio
(CCLK/SCLK) Latency in SCLKs
Burst of 4 Latency in SCLKs
Burst of 8