Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SPORT Registers
11-12 ADSP-BF535 Blackfin Processor Hardware Reference
• Endian Format Select.
SPORTx_TX_CONFIG[4]
(
SENDN
). The
DTYPE
,
SENDN
, and
SLEN
bits configure the format of the data words trans-
mitted over the SPORTs. The
SENDN
bit selects the endian format
(0=serial words are transmitted MSB first, 1=serial words are trans-
mitted LSB first).
• Serial Word Length Select.
SPORTx_TX_CONFIG[8:5]
(
SLEN
). The
DTYPE
,
SENDN
, and
SLEN
bits configure the format of the data words
transmitted over the SPORTs. The serial word length (the number
of bits in each word transmitted over the SPORTs) is calculated by
adding 1 to the value of the
SLEN
field:
Serial Word = SLEN + 1;
The
SLEN
field can be set to a value of 2 to 15; 0 and 1 are illegal
values for this field. Two common settings for the
SLEN
field are
15, to transmit a full 16-bit word, and 7, to transmit an 8-bit byte.
The ADSP-BF535 processor is a 16-bit processor, so program
instruction or DMA engine loads of the
TX
data register always
move 16 bits into the register; the
SLEN
field tells the SPORT how
many of those 16 bits to shift out of the register over the serial link.

The frame sync signal is controlled by the Frame Sync Divider reg-
ister, not by
SLEN
. To produce a frame sync pulse on each byte or
word transmitted, the proper frame sync divider must be pro-
grammed into the Frame Sync Divider register; setting
SLEN
to 7
does not produce a frame sync pulse on each byte transmitted.
• Internal Transmit Frame Sync Select.
SPORTx_TX_CONFIG[9]
(
ITFS
). This bit selects whether the SPORT uses an internal
TFS
(if
set) or an external
TFS
(if cleared).
• Transmit Frame Sync Required Select.
SPORTx_TX_CONFIG[10]
(
TFSR
). This bit selects whether the SPORT requires (if set) or does
not require (if cleared) a transfer frame sync for every data word.