Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 16-17
Timers
Note the period settings can be altered without similar impacts.

When a timer is running in PWM_OUT mode with the
PERIOD_CNT
bit set, and it is subsequently stopped, it does not wait
for the end of the current period before stopping. Once disabled,
the
TMRx
pin goes low, and the last PWM cycle is not completed.
To generate the maximum frequency on the
TMRx
output pin, set the
TIMERx_PERIOD
value to 2 and the
TIMERx_WIDTH
value to 1. This makes
TMRx
toggle each
SCLK
cycle, producing a duty cycle of 50%.
Single Pulse Generation
If the
PERIOD_CNT
bit in
TIMERx_CONFIG
is cleared, PWM_OUT generates
a single pulse on the
TMRx
pin. This mode can also be used to implement a
precise delay. The pulse width is defined by the Timer Width register and
the Timer Period register is not used.
At the end of the pulse the interrupt latch bit (
IRQx
) is set and the timer is
stopped automatically. If the
PULSE_HI
bit is set, an active high pulse is
generated on the
TMRx
pin. If
PULSE_HI
is not set, the pulse is active low.

The active low pulse configuration is not recommended, since the
TMRx
pin is always driven low when the timer is not running,
regardless of the
PULSE_HI
bit.
Figure 16-10. Recommended Width Update Procedure
W idt h
O ld
Per io d Pe r iod
W idt h
O ld
W idt h
N ew
P e rio d -
W idt h O ld
P e r iod -
W idth
P er iod -
W idt h Old +
W idt h Ne w -
W idt h Ne w
WIDT H = Wid th N ew
PE RIO D = Pe r io d O ld - W idt h O ld + W idth Ne w
PE RIO D = Pe r io d O ld
P e ri od