Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 450 / 1022

11-4 ADSP-BF535 Blackfin Processor Hardware Reference
A SPORT receives serial data on its
DR
input and transmits serial data on
its
DT
output. It can receive and transmit simultaneously for full duplex
operation. For both transmit and receive data, the data bits (
DR
or
DT
) are
synchronous to the serial clocks (
RCLK
or
TCLK
); this is an output if the
processor generates this clock or an input if the clock is externally gener-
ated. Frame synchronization signals
RFS
and
TFS
are used to indicate the
start of a serial data word or stream of serial words.
In addition to the serial clock signal, data must be signalled by a frame
synchronization signal. The framing signal can occur either at the begin-
ning of an individual word or at the beginning of a block of words.
Figure 11-1 shows a simplified block diagram of a single SPORT. Data to
be transmitted is written from an internal processor register to the
SPORT’s memory-mapped
SPORTx_TX
register. This data is optionally
compressed by the hardware then automatically transferred to the transmit
shift register. The bits in the shift register are shifted out on the SPORT’s
DT
pin, MSB first or LSB first, synchronous to the serial clock on the
TCLK
pin. The receive portion of the SPORT accepts data from the
DR
pin syn-
chronous to the serial clock. When an entire word is received, the data is
optionally expanded, then automatically transferred to the SPORT’s
memory-mapped
SPORTx_RX
register, where it is available to the processor.