Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 269 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 6-43
Memory
• If
DCBS=1
,
A[23]
selects Data Bank A instead of Data Bank B.
• With
DCBS=1
, the system functions more like two independent
caches, each a 16 KB, 2-Way set associative cache. Each Bank
serves an alternating set of 8 MB blocks of memory. For example,
Data Bank A caches all data accesses for the first 8 MB of memory
address range. That is, every 8 MB of range vies for the two line
entries (rather than every 16 KB repeat). Likewise, Data Bank B
caches data located above 8MB and below 16 MB.
• For example, if the application is working from a data set that is
1 MB long and located entirely in the first 8 MB of memory, it is
effectively served by only half the cache, that is, by Data Bank A,
which is a 16 KB, 2-Way set associative cache. In this instance, the
application never derives any benefit from Data Bank B.

For most applications, it is best to operate with
DCBS=0
. When
DCBS=1
, on-chip L2 memory is cached only in Data Bank A.
However, if the application is working from two data sets, located in two
memory spaces at least 8 MB apart, closer control over how the cache
maps to the data is possible. For example, if the program is doing a series
of dual-MAC operations in which both DAGs are accessing data on every
cycle, by placing DAG0’s data set in one block of memory and DAG1’s
data set in the other, the system can ensure that:
• DAG0 gets its data from Data Bank A for all of its accesses and
• DAG1 gets its data from Data Bank B.
This arrangement causes the core to use both data buses for cache line
transfer and achieves the maximum data bandwidth between the cache
and the core.
Figure 6-14 shows an example of how mapping is performed when
DCBS
=1.