Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Events and Sequencing
4-24 ADSP-BF535 Blackfin Processor Hardware Reference
System Interrupt Wakeup-Enable Register
(SIC_IWR)
The SIC provides the mapping between the peripheral interrupt source
and the Dynamic Power Management Controller (DPMC). Any of the
ADSP-BF535 processor peripherals can be configured to wake up the core
from its idled state to process the interrupt, simply by enabling the appro-
priate bit in the System Interrupt Wakeup-enable register (refer to
Figure 4-6 ). If a peripheral interrupt source is enabled in
SIC_IWR
and the
core is idled, the interrupt causes the DPMC to initiate the core wake-up
sequence in order to process the interrupt. Note that this mode of opera-
tion may add latency to interrupt processing, depending on the power
control state. For further discussion of power modes and the idled state of
the core, see
“Dynamic Power Management” on page 8-1 .
By default, all interrupts generate a wake-up request to the core. However,
for some applications it may be desirable to disable this function for some
peripherals, such as a SPORTx Transmit Interrupt.
The
SIC_IWR
register has no effect unless the core is idled. The bits in this
register correspond to those of the System Interrupt Mask (
SIC_IMASK
)
and Interrupt Status (
SIC_ISR
) registers.
After reset, all valid bits of this register are set to 1, enabling the wake-up
function for all interrupts that are not masked. Before enabling interrupts,
configure this register in the reset initialization sequence. The
SIC_IWR
register can be read from or written to at any time. To prevent spurious or
lost interrupt activity, this register should be written only when all periph-
eral interrupts are disabled.

Note the wake-up function is independent of the interrupt mask
function. If an interrupt source is enabled in
SIC_ISR
but masked
off in
SIC_IMASK
, the core wakes up if it is idled, but it does not
generate an interrupt.