Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 15-5
Programmable Flags
Flag Interrupt Mask Registers
(FIO_MASKA_C, FIO_MASKA_S,
FIO_MASKB_C, FIO_MASKB_S)
Like the Flag Set and Flag Clear registers, the Flag Interrupt Mask regis-
ters are implemented as complementary pairs of write-1-to-set and
write-1-to-clear registers. This implementation provides the ability to
enable or disable a
PFx
pin to act as a processor interrupt without requir-
ing read-modify-write accesses.
Flag Interrupt A and Flag Interrupt B are each supported by a dedicated
Flag Interrupt Mask Set register and a Flag Interrupt Mask Clear register
(see
Figure 15-4 , Figure 15-5 , Figure 15-6 , and Figure 15-7 ). Each
PFx
pin is represented by a bit in each of the four registers. Writing a 1 to a bit
in a mask set register enables interrupt generation for that
PFx
pin, while
writing a 1 to a bit in a mask clear register disables interrupt generation
for that
PFx
pin.
Interrupt A and Interrupt B operate independently. For example, writing
a 1 to a bit in the Flag Interrupt A Mask Set register does not affect Flag
Interrupt B. This facility allows
PFx
pins to generate Flag Interrupt A, Flag
Interrupt B, both Flag Interrupts A and B, or neither.
When using either rising or falling edge-triggered interrupts, the interrupt
condition must be cleared each time a corresponding interrupt is serviced
by writing a 1 to the appropriate
FIO_FLAG_C
bit.