Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Load/Store Operation
6-80 ADSP-BF535 Blackfin Processor Hardware Reference
When writing to or reading from non-memory locations such as I/O
device registers, the order of how read and write operations complete is
often significant. For example, a read of a status register may depend on a
write to a control register. If the address is the same, the read would return
a value from the write buffer rather than from the actual I/O device regis-
ter, and the order of the read and write at the register may be reversed.
Both these effects could cause undesirable side effects in the intended
operation of the program and peripheral. To ensure that these effects do
not occur in code that requires precise, or
strong , ordering of load and
store operations, synchronization instructions (
CSYNC
or
SSYNC
) should be
used.
Synchronizing Instructions
When strong ordering of loads and stores is required, as may be the case
for sequential writes to an I/O device for setup and control, use the core or
system synchronization instructions,
CSYNC
or
SSYNC
, respectively.
The
CSYNC
instruction ensures that all pending core operations have com-
pleted and the core buffer (between the processor core and the L1
memories) has been flushed before proceeding to the next instruction.
Pending core operations may include any pending interrupts, speculative
states (such as branch predictions) or exceptions.
Consider this example code sequence:
IF CC JUMP away_from_here
csync;
r0 = [p0];
away_from_here: