Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-9
External Bus Interface Unit
• Any access to an unpopulated area of an SDRAM memory bank
• Any access to SDRAM memory space before the SDC is enabled or
before the power-up sequence has been initiated
If the core requested the faulting bus operation, the bus error response
from the EBIU generates a hardware error interrupt (
IVHW
) internal to the
core (this interrupt can be masked off in the core). If PCI requested the
faulting bus operation, then the bus error is captured in that controller,
and can optionally generate an interrupt to the core. For more informa-
tion, refer to
“PCI Bus Interface” on page 13-1 . If a DMA master
requested the faulting bus operation, then the bus error is captured in that
controller and can optionally generate an interrupt to the core. For more
information, refer to
“Direct Memory Access” on page 9-1 .
Asynchronous Memory Interface
The asynchronous memory interface allows a glueless interface to a variety
of memory and peripheral types. These include SRAM, ROM, EPROM,
flash memory, and FPGA/ASIC designs. Four asynchronous memory
regions are supported. Each has a unique memory select associated with it,
shown in
Table 18-4 .
Table 18-4. Asynchronous Memory Bank Address Range
Memory Bank Select Address Start Address End
AMS[3]
2C00 0000 2FFF FFFF
AMS[2]
2800 0000 2BFF FFFF
AMS[1]
2400 0000 27FF FFFF
AMS[0]
2000 0000 23FF FFFF