Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 13-7
PCI Bus Interface
to the EAB bus is put into the master TX FIFO to be put onto the PCI
AD bus during the data phase. For reads, the PCI AD bus data is placed
into the master RX FIFO during the data phase.
Each of the data FIFOs is 8

32-bit words deep. The transaction FIFO is
4 transactions deep. Writes are posted as long as there is room in both the
transaction and the TX data FIFOs. Reads are delayed (slave inserts wait
states) until there is room in the transaction FIFO, then until the read
transaction makes it through to the PCI side of the FIFO, and then until
the data is returned through the RX FIFO. Thus, reads from PCI space
clear all three of the FIFOs.
If the transaction FIFO is full, all transactions are delayed until the next
spot in the FIFO is opened. Even if the transaction FIFO only has one ele-
ment in it, the TX FIFO could be either full or not have enough space for
the size burst being attempted, so the write is again delayed. Three status
bits have been provided in the
PCI_STAT
register that let you interrogate
whether the TX FIFO is full or empty and whether the transaction FIFO
is full. The PCI Master TX FIFO Empty status bit is sticky and can be
masked by the
PCI_ICTL
register to generate an interrupt to improve effi-
ciency when doing burst writes to PCI.
Outbound Error Detection and Reporting
All addresses between 0xE000 0000 and 0xEEFF FFFF are decoded to
select the PCI interface, but only part of this space is valid. There are four
windows in this space that have been marked for specific use by the PCI
interface. Three of these are defined in
Table 13-1 . The fourth consists of
the PCI configuration registers, from 0xEEFF FF00 through
0xEEFF FFFB. Any accesses made between these four valid areas (that is,
above 0xE000 0000, below 0xEEFF FFFF, and not within one of the win-
dows) results in an error. The logic in the PCI module generates a bus
error and completes the transaction without actually reading or writing
any data. The Unsupported EAB Access sticky bit in the
PCI_STAT
register
is set, and causes an interrupt if masked to do so in the
PCI_ICTL
register.