Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 12-5
UART Port Controller
The Break Interrupt (
BI
), Overrun Error (
OE
), Parity Error (
PE
) and Fram-
ing Error (
FE
) bits are cleared when the UART Line Status register
(
UARTx_LSR
) is read. The Data Ready (
DR
) bit is cleared when the UART
Receive Buffer register (
UARTx_RBR
) is read. Because of the destructive
nature of these read operations, special care should be taken. See “Specula-
tive Load Execution” on page 6-81 and “Conditional Load Behavior” on
page 6-82 for more information.
UARTx Transmit Holding Registers (UARTx_THR)
A write to the UARTx Transmit Holding register (
UARTx_THR
), shown in
Figure 12-4 , initiates the transmit operation. The data is moved to the
internal Transmit Shift register (
TSR
) where it is shifted out at a baud rate
equal to
SCLK/(16

Divisor
) with start, stop, and parity bits appended as
required. All data words begin with a 1-to-0-transition start bit. The
transfer of data from
UARTx_THR
to the Transmit Shift register sets the
Transmit Holding Register Empty (
THRE
) status flag in the UARTx Line
Status register (
UARTx_LSR
).
The
UARTx_THR
register is mapped to the same address as
UARTx_RBR
and
UARTx_DLL
. To access
UARTx_THR
, the
DLAB
bit in
UARTx_LCR
must be
cleared. When the
DLAB
bit is cleared, writes to this address target the
UARTx_THR
register, and reads from this address return the
UARTx_RBR
register.
Note that data is transmitted and received least significant bit first (bit 0)
followed by the most significant bits.
Figure 12-4. UARTx Transmit Holding Registers
Transmit Hold[7:0]
7 6 5 4 3 2 1 0
0 0 0 0 0 0
Reset = 0x00
0 0
UARTx Transmit Holding Registers (UARTx_THR)
WO
For MMR assignments,
see
Table 12-3 .