Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 568 / 1022

Device Mode Operation
13-6 ADSP-BF535 Blackfin Processor Hardware Reference
Outbound Transactions (ADSP-BF535 Processor as
PCI Initiator)
This section describes outbound transactions with the ADSP-BF535 pro-
cessor as the PCI initiator.
General Outbound Operation
Read and write transactions to PCI are achieved by first writing to the
appropriate Base Address register to position the mapping windows in
PCI address space. Write to the
PCI_MBAP
register for memory accesses, to
the
PCI_IBAP
register for I/O accesses, or to the
PCI_CBAP
register for con-
figuration accesses. After writing to the appropriate register, a read or
write to the appropriate data window initiates a PCI transaction.
For memory and I/O accesses, the address put onto the PCI Address/Data
bus (PCI AD) is a concatenation of the upper bits of the Base Address
pointer (
MBAP
or
IBAP
) and the lower bits of the load or store target
address. These lower bits are actually the offset into the static-sized PCI
Memory or I/O windows.
Table 13-1 shows the PCI data windows for
outbound reads and writes.
For all outbound read and write transactions, the control signals of the
transactions are placed into a FIFO that is written in the
SCLK
domain and
read by the PCI core in the PCI clock domain. For writes, the data written
Table 13-1. Data Windows in EAB for Outbound Transactions
Name Lower Address Upper Address Size
Memory Data Window 0xE000 0000 0xE7FF FFFF 128 MB
I/O Data Window 0xEEFE 0000 0xEEFE FFFF 64 KB
Config Data Port 0xEEFF FFFC 0xEEFF FFFF 1 Word (32 bits)