Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-73
External Bus Interface Unit
After the prefetch reads start, they continue until one of these conditions
is met:
• The SDC read buffer is full.
• The AMC has a pending request and the AMC has priority over
prefetches (
PFP = 0
in the SDRAM Memory Global Control
register).
• An Auto-Refresh or Self-Refresh request occurs.
• Another SDC access occurs from the core, a DMA, or PCI.
• Prefetching is disabled (
PFE
=
0
in the SDRAM Memory Global
Control register).
If a cache line fill access starts to the address of the line stored in the read
buffer, data from the read buffer starts being returned every cycle. At the
same time, the SDC determines the address of the first word which is not
in the read buffer and then starts this transfer from the SDRAM. As long
as there are enough words that hit in the read buffer to cover the latency of
reading the remaining addresses that did not hit in the read buffer, the
maximum throughput can be achieved. If there are not enough hits to
cover the latency, wait states are inserted in the middle of the cache line
fill until read data for the remaining words can be returned. When the
read accesses for the words that were not in the read buffer complete, the
SDC begins launching prefetch reads of the next sequential line in
memory.
If a cache line fill access starts to an address that does not match any of the
addresses of the data in the read buffer (a read buffer miss), the read buffer
data is invalidated, the accesses required to service the cache line fill are
launched, and then prefetches of the next line begin.