Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-84 ADSP-BF535 Blackfin Processor Hardware Reference
Table 18-20. Throughput for Accesses to 16-Bit Wide SDRAM
Accesses Read/
Write
Page Hit/Miss
1 Throughput
L1 Cache Line Fill
(

12 half word Read Buffer Hit)
Read Page Hit 8 words/8 cycles
L1 Cache Line Fill
(N half word Read Buffer Hit, where
N < 12) Read Page Hit N half word hit: 8
words/(21-N) cycles
L1 Cache Line Fill
(Read Buffer Miss) Read Page Hit 8 words/21 cycles
L1 Cache Copyback Write Page Hit 8 words/24 cycles
DMA Burst Read (4 words) Read Page Hit 4 words/13 cycles
DMA Burst Write (4 words) Write Page Hit 4 words/12 cycles
DMA Burst Read (8 words) Read Page Hit 8 words/21 cycles
DMA Burst Write (8 words) Write Page Hit 8 words/20 cycles
Single Read Read Page Hit 1 word/7 cycles
Single Write Write Page Hit 1 word/3 cycles
L1 Cache Line Fill
(Read Buffer Miss) Read Page Miss 8 words/25 cycles
L1 Cache Copyback Write Page Miss 8 words/28 cycles
DMA Burst Read (4 words) Read Page Miss 4 words/17 cycles
DMA Burst Write (4 words) Write Page Miss 4 words/16 cycles
DMA Burst Read (8 words) Read Page Miss 8 words/25 cycles
DMA Burst Write (8 words) Write Page Miss 8 words/24 cycles
Single Read Read Page Miss 1 words/11 cycles
Single Write Write Page Miss 1 words/7 cycles
1 Page-Miss Penalty = t
RP
+ t
RCD