Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Events and Sequencing
4-18 ADSP-BF535 Blackfin Processor Hardware Reference
Note that the word event describes all five types. The Event Controller
manages fifteen events in all: Emulation, Reset, NMI, Exception, and
eleven interrupts.
An interrupt is an event that changes normal processor instruction flow
and is asynchronous to program flow. In contrast, an exception is a soft-
ware initiated event whose effects are synchronous to program flow.
The event system is nested and prioritized. Consequently, several service
routines may be active at any time, and a low priority event is preempted
by one of higher priority.
The ADSP-BF535 processor employs a two-level event control mecha-
nism. The ADSP-BF535 processor System Interrupt Controller (SIC)
works with the Core Event Controller (CEC) to prioritize and control all
system interrupts. The SIC provides mapping between the many periph-
eral interrupt sources and the prioritized general-purpose interrupt inputs
of the core. This mapping is programmable, and individual interrupt
sources can be masked in the SIC.
The CEC supports nine general-purpose interrupts (
IVG7
-
IVG15
) in addi-
tion to the dedicated interrupt and exception events that are described in
Table 4-6 . It is recommended that the lowest two priority interrupts
(
IVG14
and
IVG15
) be reserved for software interrupt handlers, leaving
seven prioritized interrupt inputs (
IVG7
-
IVG13
) to support the
ADSP-BF535 processor system. Refer to Table 4-6 .
Note the System Interrupt to Core Event mappings shown are the default
values at reset and can be changed by software.