Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 334 / 1022

Clocking
8-2 ADSP-BF535 Blackfin Processor Hardware Reference
All synchronous peripherals derive their timing from
SCLK
. For example,
the Universal Asynchronous Receiver/Transmitter (UART) clock rate is
determined by further dividing the
SCLK
signal. Several of the
ADSP-BF535 peripherals, such as Universal Serial Bus (USB), Peripheral
Control Interface (PCI), and Real-Time Clock (RTC), have their own
clock inputs that operate asynchronously to
SCLK
.
Phase Locked Loop and Clock Control
To provide the clock generation for the core and system, the
ADSP-BF535 processor uses an analog PLL with programmable state
machine control.
The PLL design serves a wide range of applications. It emphasizes embed-
ded and portable applications in which performance, flexibility and
control of power dissipation are key features. This broad range of applica-
tions requires a wide range of frequencies for the clock generation
circuitry. The PLL interacts with the Dynamic Power Management Con-
troller (DPMC) block to provide power management functions for the
ADSP-BF535 processor.
PLL Overview
The PLL supports a wide range of multiplier ratios, achieving 1–31x mul-
tiplication of the input clock,
CLKIN
. To achieve this wide multiplication
range, the ADSP-BF535 processor uses a combination of programmable
dividers in the PLL feedback circuit and output configuration blocks.
Figure 8-1 illustrates a conceptual model of the PLL circuitry, configura-
tion inputs, and resulting outputs.
The input clock,
CLKIN
, is a square wave derived from a crystal oscillator
or external reference clock. The Voltage Controlled Oscillator (
VCO
) is an
intermediate clock from which the core clock (
CCLK
) and system clock
(
SCLK
) are derived.