Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-45
External Bus Interface Unit
Once the SDRAM device enters into Self-Refresh mode, the SDRAM
controller asserts the
SDSRA
bit in the SDRAM Control Status register
(
EBIU_SDSTAT
). The SDRAM controller ignores another Self-Refresh
request (
SRFS = 1
) when the SDRAM device is already in Self-Refresh
mode.
The SDRAM device exits Self-Refresh mode only when the SDC receives
a core, DMA, or PCI access request.
Note once the
SRFS
bit is set to 1, the SDC enters Self-Refresh mode when
it finishes pending accesses. There is no way to cancel the entry into
Self-Refresh mode.
Setting the SDRAM Buffering Timing Option (EBUFE)
To meet overall system timing requirements, systems that employ several
SDRAM devices connected in parallel may require buffering between the
ADSP-BF535 processor and multiple SDRAM devices. This buffering
generally consists of a register and driver.
To meet such timing requirements, the SDC supports pipelining of
SDRAM address and control signals.
The
EBUFE
bit in the
EBIU_SDGCTL
register enables this mode:
EBUFE = 0
Disable external buffering timing
EBUFE = 1
Enable external buffering timing
When
EBUFE = 1
, the SDRAM controller delays the data in write accesses
by one cycle, enabling external buffer registers to latch the address and
controls. In read accesses, the SDRAM controller samples data one cycle
later to account for the one-cycle delay added by the external buffer regis-
ters. When external buffering timing is enabled, the latency of all accesses
is increased by one cycle.