Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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9-2 ADSP-BF535 Blackfin Processor Hardware Reference
• USB DMA Controller
• SPI0 DMA Controller
• SPI1 DMA Controller
• UART0 RCV Controller
• UART1 RCV Controller
• UART0 XMT Controller
• UART1 XMT Controller
• Memory DMA Controller
This chapter describes the features common to all the DMA channels and
how DMA operations are set up. For specific peripheral features, see the
appropriate peripheral chapter for additional information. Performance
and bus arbitration for DMA operations can be found in
“DAB Perfor-
mance” on page 7-11 .
DMA transfers on the ADSP-BF535 processor can be descriptor based or
autobuffer based. Descriptor based DMA transfers require a set of param-
eters stored within memory to initiate a DMA sequence. This sort of
transfer allows chaining multiple DMA sequences together. In descriptor
based DMA operations, a DMA channel can be programmed to set up and
start another DMA transfer automatically after the current sequence com-
pletes. Autobuffer based DMA allows the processor to program DMA
control registers directly to initiate a DMA transfer. Upon completion,
the control registers are automatically updated with their original setup
values.