Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Events and Sequencing
4-28 ADSP-BF535 Blackfin Processor Hardware Reference
Although this register can be read from or written to at any time (in
Supervisor mode), it should be configured in the reset initialization
sequence before enabling interrupts.

SIC_IMASK[31]
provides a mask for the core double-fault
condition:
• If the condition is unmasked and the core detects a double-fault
condition, a hardware reset is generated.
• If the condition is masked and the core detects a double-fault con-
dition, core behavior may be unreliable.
Figure 4-8. System Interrupt Mask Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
System Interrupt Mask Register (SIC_IMASK)
Reset = 0x0000 0000
Timer 2 Interrupt
For all bits, 0 - Interrupt masked, 1 - Interrupt enabled.
PF Interrupt A
PF Interrupt B
Memory DMA Interrupt
Software Watchdog Timer
Interrupt
Real-Time Clock Interrupt
USB Interrupt
PCI Interrupts
SPORT0 RX Interrupt
SPORT0 TX Interrupt
SPORT1 RX Interrupt
SPORT1 TX Interrupt
Timer 1 Interrupt
Timer 0 Interrupt
UART1 TX Interrupt
UART1 RX Interrupt
UART0 TX Interrupt
UART0 RX Interrupt
SPI1 Interrupt
SPI0 Interrupt
Core Double-fault
Reset Mask
0xFFC0 0C10