Interrupts With and Without Nesting
4-48
ADSP-BF535 Blackfin Processor Hardware Reference
Interrupts With and Without Nesting
Interrupts are handled either with or without nesting. If interrupts do not
require nesting, all interrupts are disabled during the interrupt service
routine. Note, however, that emulation, NMI, and exceptions are still
accepted by the system.
When the system does not need to support nested interrupts, there is no
need to store the return address held in
RETI
. Only the portion of the
machine state used in the interrupt service routine must be saved in the
Supervisor stack. To return from a non-nested interrupt service routine,
only the
RTI
instruction must be executed, because the return address is
already held in the
RETI
register.
Figure 4-15
shows an example of interrupt handling where interrupts are
globally disabled for the entire interrupt service routine.
If nested interrupts are desired, the return address to the interrupted point
in the original interrupt service routine (ISR) must be explicitly saved and
subsequently restored when execution of the nested ISR has completed.
Nesting is enabled by pushing the return address currently held in RETI
to the Supervisor stack (
[--SP] = RETI
), which is typically done early in
the ISR prolog of the lower priority interrupt. This clears the global inter-
rupt disable bit
IPEND[4]
, enabling interrupts. Next, all registers that are
modified by the interrupt service routine are saved onto the Supervisor
stack. Processor state is stored in the Supervisor stack, not in the User
stack. Hence, the instructions to push
RETI
(
[--SP]=RETI
) and pop
RETI
(
RETI=[SP++]
) use the Supervisor stack.
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...