Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 258 / 1022

Memory Architecture
6-32 ADSP-BF535 Blackfin Processor Hardware Reference
R0.L = 0;
R0.H = 0;
[I1] = R0;
/* The cache lines come out of reset in a random state. The valid
bits of each line must be set to zero at initialization. */
/* Explanation: The invalidation routine is as follows: */
/* Cache setup: */
/* I-CACHE: */
/* 4 sub-banks, */
/* each sub-bank has 4 ways, */
/* each way has 32 lines, */
/* each line (or set) has 4 double words. */
/* Routine: */
/* - Take way 0, and way 1 */
/* - Inner loop: */
/* Invalidate all sets (cache lines) in sub- bank for way 0
and way 1
*/
/* Instruction Cache has 32 sets (cache lines), hence loop
count is 32
*/
/* - Outer loop: */
/* Increment sub-banks */
/* repeat inner loop */
/* do it 4 times because of 4 sub-banks. */
/* - Repeat again for way 2, way 3 */
R2 = 32; /* Need to increment the set index every loop (Should
be 64 for D-cache) */
R3.L = 0; /* sub-bank increment, at the end of inner loop */
R3.H = 1;
P4 = 4; /* Number of sub-bank - also outer loop counter (Should
be 2 for D-cache) */
P3 = R2; /* Inner loop counter (Number of set index) */