Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 8-7
Dynamic Power Management
PLL Memory-Mapped Registers (MMRs)
The user interface to the PLL is through three MMRs:
• The PLL Control register (
PLL_CTL
)
• The PLL Status register (
PLL_STAT
)
• The PLL Lock Count register (
PLL_LOCKCNT
)
The
PLL_CTL
register is a 32-bit MMR and must be accessed with aligned
32-bit reads/writes. The
PLL_STAT
and
PLL_LOCKCNT
registers are 16-bit
MMRs and must be accessed with aligned 16-bit reads/writes.
PLL Control Register (PLL_CTL)
The PLL Control register (
PLL_CTL
), shown in Figure 8-2 , controls opera-
tion of the PLL. Note that changes to the
PLL_CTL
register do not take
effect immediately. In general, the
PLL_CTL
register is first programmed
with new values, and then a specific PLL programming sequence must be
executed to implement the changes. See
“PLL Programming Sequence” on
page 8-17 .
These fields of the
PLL_CTL
register are used to control the PLL:
•
SSEL[1:0]
– The
SCLK
Select (
SSEL
) field defines the core clock
(
CCLK
) to system clock (
SCLK
) divider ratio. Upon reset, the value
for this field is sensed from the
SSEL
pins.
•
MSEL[6:0]
– The Multiplier Select (
MSEL
) field defines the input
clock (
CLKIN
) to core clock
(CCLK
) multiplier. Upon reset, the value
for this field is sensed from the
MSEL
pins.
•
BYPASS
– This bit is used to bypass the PLL. When the PLL is
bypassed,
CCLK
runs at half the frequency of
CLKIN
. Upon reset, the
value for this field is sensed from the
BYPASS
pin.