Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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G-4 ADSP-BF535 Blackfin Processor Hardware Reference
CAS (Column Address Strobe).
A signal sent from the memory management unit (MMU) to a DRAM
device to indicate that the column address lines are valid.
CAS latency (also t
AA
, t
CAC
, CL).
The column address strobe (CAS) latency is the delay in clock cycles
between when the SDRAM detects the read command and when it pro-
vides the data at its output pins. The CAS latency is programmed in the
SDRAM Mode register during the power-up sequence.
The speed grade of the SDRAM and the
SCLK[0]
frequency determine the
value of the CAS latency. The SDC can support CAS latency of 2 or 3
clock cycles. The selected CAS latency value must be programmed into
the SDRAM Memory Global Control register (
EBIU_SDGCTL
) before the
SDRAM power-up sequence. See “SDRAM Memory Global Control Reg-
ister (EBIU_SDGCTL)” on page 18-37 .
CBR (CAS Before RAS) memory refresh.
DRAM devices have a built-in counter for the refresh row address. By
activating CAS before activating RAS, this counter is selected to supply
the row address instead of the address inputs.
CEC.
See Core Event Controller
circular buffer addressing.
The process by which the DAG “wraps around” or repeatedly steps
through a range of registers.
companding
(compressing/expanding). The process of logarithmically encoding and
decoding data to minimize the number of bits that must be sent.