Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 1-13
Introduction
The controller maintains all banks as a contiguous address space. The pro-
cessor sees this as a single address space, even if different size devices are
used in different banks. This allows a system to be upgraded with either
similar or different memories.
A set of programmable timing parameters is available to configure
SDRAM banks to support slower memory devices. The memory banks can
be configured as either 32 bits wide for maximum performance and band-
width or 16 bits wide for minimum device count and lower system cost.
All four banks share common SDRAM control signals and have their own
bank select lines, providing a glueless interface for most system
configurations.
Asynchronous Controller
The asynchronous memory controller provides a configurable interface for
up to four separate banks of memory or I/O devices. Each bank can be
independently programmed with different timing parameters. This allows
connection to a wide variety of memory devices, including SRAM, ROM,
and flash EPROM, as well as I/O devices that interface with standard
memory control lines. Each bank occupies a 64 Mbyte window in the pro-
cessor address space, but if not fully populated, these are not made
contiguous by the memory controller. The banks can also be configured as
16- or 32-bit wide buses for interfacing to a range of memories and I/O
devices for high performance or low cost and power.
PCI Interface
The ADSP-BF535 processor provides a 33 MHz, 32-bit, revision 2.2
compliant Peripheral Component Interconnect (PCI) interface. The PCI
provides a bus bridge function between the processor core and on-chip
peripherals and an external PCI bus. The PCI interface of the
ADSP-BF535 processor supports two PCI functions: