Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-77
External Bus Interface Unit
Bank Activate Command
The Bank Activate command is required if the next data access is in a dif-
ferent page. The SDC executes the Precharge command, followed by a
Bank Activate command, to activate the page in the desired SDRAM
internal bank. Only one SDRAM internal bank in each external bank may
be active at a time.
Load Mode Register Command
The Load Mode Register command initializes SDRAM operation parame-
ters. This command is a part of the SDRAM power-up sequence. Load
Mode Register uses the address bus of the SDRAM as data input. The
power-up sequence is initiated by writing 1 to the
PSSE
bit in the SDRAM
Memory Global Control register (
EBIU_SDGCTL
) and then writing or read-
ing from any enabled address within the SDRAM address space to trigger
the power-up sequence. The exact order of the power-up sequence is
determined by the
PSM
bit of the
EBIU_SDGCTL
register.
The Load Mode Register command initializes these parameters:
• Burst length = 1, bits 2-0, always zero
• Wrap type = sequential, bit 3, always zero
• Ltmode = latency mode (CAS latency), bits 6-4, programmable in
the
EBIU_SDGCTL
register
• Bits 14-7, always zero
While executing the Load Mode Register command, the unused address
pins are set to zero. During the two
SCLK
cycles following Load Mode Reg-
ister, the SDC issues only NOP commands.