Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 20-29
Blackfin Processor’s Debug
The upper 16 bits of the DMA Bus Control Comparator register provide a
cycle count function that helps determine when a given DMA access has
occurred. The counter is clocked by the DMA bus clock.
The counter can be cleared in either of two ways:
• By a hardware reset
• By clearing the Enable Compare and Count bit (
DB_CCOMP[0]
)
When enabled, the counter increments from 0 to a maximum value of
65,535 until a match is detected or the compare-and-count function is
disabled. A comparison match freezes the counter within two cycles of the
assertion of
CH
.
DMA Bus Address Comparator Register
(DB_ACOMP)
Figure 20-18 shows the DMA Bus Address Comparator register
(
DB_ACOMP).
Program into this register the DMA address that is associated
with the type of bus information that you wish to detect.
Figure 20-18. DMA Bus Address Comparator Register
DMA Bus Address Comparator Register (DB_ACOMP)
Read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA Address[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA Address[31:16]
Reset = 0x0000 0000 0xFFC0 4884